As known, in electrically programmable non-volatile memory devices integrated on semiconductor and in particular of the flash type there is a need to power a circuitry section with different voltages depending on the type of operation to be performed.
For example, during the reading and decoding phase of a row of the memory matrix the row decoding block is powered with a standard supply voltage Vcc of approximately 5V.
But during the programming phase the same block is powered with a programming voltage Vp higher than the supply voltage Vcc. The programming voltage can be generated in the memory circuit or supplied by an external power supply connected to a pin of the memory circuit.
A prior art solution for providing switching circuitry to switch between power supplies is illustrated in the annexed FIG. 1.
This solution calls for switching circuitry 20 comprising two circuit branches 22 and 23 each having two P-channel MOS transistors arranged in mutual series.
For the first branch 22 the transistors MA and MB are indicated while for the second branch 23 the transistors MC and MD are indicated.
It is known that biasing of the well regions of the P-channel transistors requires particular precautions since an erroneous well potential can generate dangerous latch-up phenomena.
The well region of the first transistor MA of the first branch is connected to a first voltage reference SUPPLY1 which can be made equal to the standard supply voltage Vcc while the well region of the first transistor MC of the second branch is connected to a second reference voltage SUPPLY2.
The well regions of the two remaining transistors MB and MD are connected to a common circuit node C on which is present the same voltage VSW.
For no junction to be biased directly it is sufficient that the interconnection nodes A and B between the first and second transistors of each branch, i.e. between MA and MB on one side and MC and MD on the other side, be supplied by the lower of the voltages SUPPLY1 and SUPPLY2.
In other words, it is basically important for correct operation of the circuit that the voltage on the interconnection nodes A, B remain higher than that on the common node C.
There is provided for this purpose the presence of the N-channel transistors M1, M2 for the first branch and M3, M4 for the second branch. These transistors impose on the corresponding interconnection node A or B the lower voltage between the two possible supply voltages SUPPLY1 and SUPPLY2.
Although advantageous in some ways, this solution is not without some shortcomings as set forth below.
The bias of the interconnection nodes A and B is effective only when the difference between the two supply voltages SUPPLY1 and SUPPLY2 is appreciable. But when the values of these two voltages are very close, e.g. if they differ only by the threshold of an N-channel transistor, the body effect causes a floating behavior of the interconnection node.
Essentially, a switching phase calling for the discharge of the common node C from a high voltage, e.g. 12V, to a lower supply voltage, e.g. Vcc, would cause direct biasing of the first transistor MA if the difference between the two supply voltages SUPPLY1 and SUPPLY2 were less than 2V.
In addition, since there is a need to reduce the overall voltage drop on the switching circuitry, in the switching circuitry there are normally used big transistors with capacitances on the order of hundreds of picofarads. The switch causes a violent discharge of the common node C but if the node C is to return to the higher potential the inertia of the transistors slows the circuit.